Modern high-speed serial transceivers have received wide application in cross-chip and serial data communication networks. For example, high-speed serial transceivers are used in applications such as advanced memory buffer (AMB) technology. In contrast to their parallel counterparts, high-speed serial transceivers have the capability of extracting a clock signal encoded within a received data stream, allowing for network synchronization over a single data channel. This capability has consequently eliminated the requirement of sending data and synchronization clock signals over multiple channels. Phase locked loops (PLLs) are utilized in data communications and telecommunications applications to lock onto a frequency and phase of a signal.
The transceiver utilizes the PLL for both a transmitter side and a receiver side of the transceiver. In the transmitter side, the PLL is used to serialize the parallel data and clock it out on the media. In the receiver side, the PLL is used to recover the data and de-serialize the input data. For many cases, a common reference clock is used. Unfortunately, unavoidable routing delays result when distributing the reference clock to both ends of the serial link. Certain bandwidth parameters of the PLL, such as the −3 dB jitter attenuation (also sometimes referred to herein as “−3 dB bandwidth”) and the jitter peaking, can be critical for inter-operation considerations.
The bandwidth parameters of both the transmitter PLL and the receiver PLL should be within a given range to avoid excessive jitter, which can be detrimental to optimal or even satisfactory operation of the transceiver. Having clear knowledge of the phase locked loop performance is imperative for the successful application of advanced memory buffer products, as well as other products that utilize high-speed serial links.